Product Code Database
Hexagon is the brand name for a family of digital signal processor (DSP) and later neural processing unit (NPU) products by Qualcomm. Hexagon is also known as QDSP6, standing for “sixth generation digital signal processor.” According to Qualcomm, the Hexagon architecture is designed to deliver performance with low power over a variety of applications.
Each version of Hexagon has an instruction set and a micro-architecture. These two features are intimately related.
Hexagon is used in Qualcomm Snapdragon chips, for example in smartphones, cars, wearable devices and other mobile devices and is also used in components of cellular phone networks.
Assemblers and compilers that translate computer programs into streams of instructions – bit streams - that the device can understand and carry out (execute). As an instruction stream executes, the integrity of system function is supported by the use of instruction privilege levels. Privileged instructions have access to more resources in the device, including memory. Hexagon supports privilege levels.
Originally, Hexagon instructions operated on integer numbers but not floating point numbers, but in v5 floating point support was added.
The processing unit which handles execution of instructions is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution unit every clock. Porting LLVM to a Next Generation DSP, L. Taylor Simpson (Qualcomm) // LLVM Developers’ Meeting: 11/18/2011
According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSPWill Strauss, Forward Concepts. Wireless/DSP Market Bulletin: Qualcomm Leads in Global DSP Silicon Shipments // Forward Concepts: "In calendar year 2011, Qualcomm shipped a reported 521 million MSM chip shipments and we estimate that an average of 2.3 of its DSP cores in each unit resulted in 1.2 billion DSPs shipped in silicon. This (calendar) year, we estimate that the company will ship an average of 2.4 DSP cores with each (more complex) MSM chip." (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licensable DSP market[3]; [4]; Ceva grabs 90% of DSP IP market, 2012).
The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, very long instruction word (VLIW), single instruction, multiple data (SIMD),Hexagon v2 Programmers Reference and instructions geared toward efficient signal processing. Hardware multithreading is implemented as Barrel processor temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5. Faster 128-EEA3 and 128-EIA3 Software, Roberto Avanzi and Billy Bob Brumley (Qualcomm Research), Cryptology ePrint Archive: Report 2013/428, 2 Jul 2013. Page 9. Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions. Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading // Linley Gwennap, Microprocessor Report, August 2013
At Hot Chips 2013 Qualcomm announced details of their Hexagon 680 DSP. Qualcomm announced Hexagon Vector Extensions (HVX). HVX is designed to allow significant compute workloads for advanced imaging and computer vision to be processed on the DSP instead of the CPU. In March 2015 Qualcomm announced their Snapdragon Neural Processing Engine SDK which allow AI accelerator using the CPU, GPU and Hexagon DSP.
Qualcomm's Snapdragon 855 contains their 4th generation on-device AI engine, which includes the Hexagon 690 DSP and Hexagon Tensor Accelerator (HTA) for AI accelerator. Snapdragon 865 contains the 5th generation on-device AI engine based on the Hexagon 698 DSP capable of 15 trillion operations per second (TOPS). Snapdragon 888 contains the 6th generation on-device AI engine based on the Hexagon 780 DSP capable of 26 TOPS. Snapdragon 8 contains the 7th generation on-device AI engine based on the Hexagon DSP capable of 52 TOPS and up to 104 TOPS in some cases.
They are also used in some femtocell processors of Qualcomm, including FSM98xx, FSM99xx and FSM90xx. Qualcomm Aims Hexagon at Femtocells, October 31, 2011. Linley Gwennap// Linley WIRE
In May 2018 wolfSSL added support for using Qualcomm Hexagon. This is support for running wolfSSL crypto operations on the DSP. In addition to use of crypto operations a specialized operation load management library was later added.
Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.
QDSP5 usage:
QDSP6 (Hexagon) usage:
D - decode; E - encode
FHD = FullHD = 1080p = 1920x1080px
HD = 720p which can be 1366x768px or 1280x720px
This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.
Software support
Operating systems
The porting of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"
(restricted access)) and was merged with the 3.2 release of the kernel. Linux Kernel 3.2 Release Notes "1.4. New architecture: Hexagon" The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.Richard Kuo, Hexagon MiniVM // linux.ports.hexagon, 25 Apr 2013 Hexagon MiniVM // CodeAurora (Qualcomm)
Compilers
Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum. Hexagon/HVX V66 ISA support was added in 8.0.0 release of LLVM. There is also a non-FSF maintained branch of GCC and binutils.
Adoption of the SIP block
Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006. Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4, 10/12/2011 by John Oram. Quote: "Hexagon DSPs have been in Snapdragon chips since 2006." QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core // InsideDSP, June 22, 2012 In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.
Third-party integration
In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.
Versions
There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800), and QDSP6 V6 (2016, in Snapdragon 820) V4 has 20 DMIPS per milliwatt, operating at 500 MHz.
600 400 400 500 Snapdragon
600600 Snapdragon
410/412/800/801536 12/28 2014 205/208/210/212
Snapdragon
425/427/429/430/435/439V50 (or QDSP6 V5.0) 28 2014 700/800 (805) Snapdragon
415/610/615/616/805546 14/28 2015 Snapdragon
450/617/625/626/632V56 (or QDSP6 V5.6) 20/28 2015 800 (808/810) Snapdragon
650/652/653/808/810642 14 2017 Snapdragon
630787 (660), 2000
(820 Qualcomm's QDSP6 v6: Imaging and Vision Enhancements Via Vector Extensions // BDTI, September 29, 2015 & 821)Snapdragon
636/660/820/821682 10 2017 Snapdragon
835683 11 2020 Snapdragon
460/662685 10/11 2018 (3 TOPS) Snapdragon
670/675/678/710/712/845/850686 6/8/11 2019 (3.3 TOPS) Snapdragon
480/480+/665/680/685/695688 8 2019 (3.6 TOPS) Snapdragon
730/730G/732G690 7 2019 (7 TOPS/
9 TOPS) Snapdragon
855/855+/860/8c/8cx/8cx Gen 2
Microsoft SQ1/SQ2692 8 2020 (5 TOPS) Snapdragon
690/720G/7c/7c Gen 2694 8 2020 (4.7 TOPS) Snapdragon
750G696 7 2020 (5.4 TOPS) Snapdragon
765/765G/768G698 7 2020 (15 TOPS) Snapdragon
865/865+/870/8cx Gen 3
Microsoft SQ3770 5/6 2021 (12 TOPS) Snapdragon
778G/778G+/780G/782G780 5 2021 (26 TOPS/
32 TOPS) Snapdragon
888/888+
/ref>4 2021 (32 TOPS)
(INT8) Snapdragon
8 Gen 1/8+ Gen 1NPU (HTP Gen 2) 4 2022 (26 TOPS)
(INT8) Snapdragon
8 Gen 2NPU (HTP Gen 3) 4 2023 (34 TOPS)
(INT8) Snapdragon
8 Gen 3/8s Gen 3NPU (HTP Gen 4) 3 2024
/ref> Snapdragon
8 EliteNPU (HTP Gen 4) 4 2024
/ref> Snapdragon
X (Plus/Elite)
Availability in Snapdragon products
Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.
65 45 45 45 45 LP 65 45 28 28 28 28 LP 28 LP 28 HPm 14 FinFET LPP
Hardware codec supported
The different video codecs supported by the Snapdragon SoCs.
Snapdragon 200 series
The different video codecs supported by the Snapdragon 200 series.
H263 VC-1 H.264 H.264 10-bit VP8 H.265 H.265 10-bit H.265 12-bit VVC VP9 VP9 10-bit AV1
Snapdragon 400 series
The different video codecs supported by the Snapdragon 400 series.
H263 VC-1 H.264 H.264 10-bit VP8 H.265 H.265 10-bit H.265 12-bit VVC VP9 VP9 10-bit AV1 Video frame rate support, decoding HD 60 fps FHD 60 fps FHD 60 fps FHD 60 fps Video frame rate support, encoding HD 60 fps FHD 60 fps FHD 60 fps FHD 60 fps
Snapdragon 600 series
The different video codecs supported by the Snapdragon 600 series.
Snapdragon 700 series
The different video codecs supported by the Snapdragon 700 series.
H263 VC-1 H.264 H.264 10-bit VP8 H.265 H.265 10-bit H.265 12-bit VVC VP9 VP9 10-bit AV1 Video frame rate, decoding HD 240 fps HD 240 fps HD 240 fps HD 480 fps FHD 120 fps FHD 120 fps FHD 120 fps ? 4K 30fps 4K 30fps 4K 30fps 4K 60fps Video frame rate support, encoding HD 240 fps HD 240 fps HD 240 fps HD 480 fps FHD 120 fps FHD 120 fps FHD 120 fps ? 4K 30fps 4K 30fps 4K 30fps ? Display and playback 10-bit HDR HDR10, HLG HDR10, HLG, HDR10+ Video recording HDR10, HLG HDR10, HLG, HDR10+ Photo recording 10-bit HDR HEIF
Snapdragon 800 series
The different video codecs supported by the Snapdragon 800 series.
MPEG-4 H263 VC-1 H.264 H.264 10-bit VP8 H.265 H.265 10-bit VP9 VP9 10-bit AV1 VVC Decoding
Frame rate HD@120 HD@240 HD@480 HD@480 HD@960 FHD@60 FHD@120 FHD@240 FHD@240 colspan="2" 4K@30 4K@60 4K@120 colspan="7" 8K@? 8K@60 Encoding
FPS HD@120 HD@240 HD@480 HD@480 HD@960 FHD@60 FHD@120 FHD@240 FHD@240 colspan="2" 4K@30 4K@60 4K@60 4K@120 colspan="8" 8K@30 Display and
playback colspan="5" HDR HDR10,
HLG HDR10, HLG,
HDR10+, Dolby Vision Video
recording colspan="6" HDR10,
HLG HDR10, HLG,
HDR10+ HDR10, HLG,
HDR10+, Dolby Vision Photo
recording colspan="9" 10-bit HDR HEIF
Code sample
This is a single instruction packet from the inner loop of a FFT:
{ R17:16 = MEMD(R0++M1)
MEMD(R6++M1) = R25:24
R20 = CMPY(R20, R8):<<1:rnd:sat
R11:10 = VADDH(R11:10, R13:12)
}:endloop0
See also
External links
target="_blank" rel="nofollow"> Introduction to Qualcomm’s QDSP Access Program // Qualcomm, 2011
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